Level shifting circuits are used in a variety of applications where voltages of varying levels (e.g., supplied by multiple voltage sources) are utilized, such as might be used in memory devices, for example. Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand. Flash memory devices typically require relatively large voltages for programming and erasing operations. For example, a Flash memory device may have a supply voltage (e.g., Vcc) of 3V but require a program voltage (e.g., Vpp) of 20V to be used during programming and/or erase operations on the memory device.
FIG. 1A illustrates a typical prior art level shifting circuit 100. Level shifting circuits can be used to interface between components and/or blocks of circuitry which are powered by different supply voltages. For example, a portion of the control circuitry (e.g., logic circuitry) in a memory device may operate at a Vcc of 3V. However, this logic circuitry must be able to interface (e.g., level shift signals) with components coupled to and configured to switch high voltages, such as components configured to apply programming and/or erase voltages to memory cells in the memory device, for example.
The circuit shown in FIG. 1A includes an enhancement mode n-channel field effect transistor (NFET) 102 connected to an enhancement mode p-channel field effect transistor (PFET) 104 at Vout node 124, which comprises Vout of the circuit 100. The gate of the enhancement mode NFET 102 is connected to Vcc 120. A depletion mode NFET 106 is connected between the enhancement mode PFET 104 and a high voltage source Vpp 108 to be switched. The gate of the depletion mode NFET 106 is connected to Vout node 124. The substrate or well of the enhancement mode PFET 104 is connected to the depletion mode NFET 106 at node 128. A first inverter INV1 114 inverts the input voltage (VIN) signal 118. The output of the first inverter 114 is connected to the gate of the enhancement mode PFET 104 and to the input of a second inverter INV2 116 by node 122. The output of the second inverter INV2 116 is connected to the enhancement mode NFET 102 by node 126.
A voltage level representative of a logical ‘0’ (e.g., ground potential) at VIN 118 is inverted to a logical ‘1’ (e.g., Vcc), i.e., an opposite logic level, at the output of the first inverter INV1 114 at node 122. The logical 1 on node 122 turns off the enhancement mode PFET 104. The second inverter INV2 116 inverts the logical 1 at node 122 to a logical 0 at node 126. As the gate of the enhancement mode NFET 102 is biased to Vcc 120 (e.g., 3V), the logical 0 (e.g., ground potential) at node 126 causes the enhancement mode NFET 102 to turn on pulling the Vout node 124 to a low potential. Thus, a logical 0 at VIN causes the enhancement mode NFET 102 to act as a pass through gate resulting in a logical 0 at Vout node 124.
A logical 1 (e.g., Vcc) at VIN is inverted by the first inverter INV1 114 to a logical 0 at node 122. This enables the enhancement mode PFET 104 whose gate is connected to node 122. The logical 0 at node 122 causes the second inverter INV2 to drive its output to a logical 1 (e.g., 3V) at node 126. The logical 1 at node 126 and Vcc 120 on the gate of the enhancement mode NFET 102 disables the enhancement mode NFET 102. Although the enhancement mode NFET 102 is disabled, node 124 is initially biased up to (Vcc−Vtn) due to the presence of Vcc on the gate of enhancement mode NFET 102, where Vtn is the threshold voltage of enhancement mode NFET 102. This initial bias condition begins to bias the gate of depletion mode NFET 106 which begins to turn on. As the depletion mode NFET 106 begins to turn on, Vout is pulled up to Vpp through the activated enhancement mode PFET 104 and the activated depletion mode NFET 106.
FIG. 1B shows a typical example of the relationship between input and output levels of the circuit shown in FIG. 1A. It can be seen that as VIN of the top waveform increases to Vcc (e.g., 3V) the lower waveform Vout rises to Vpp (e.g., 20V). It should be noted that the waveforms shown in FIG. 1B are not necessarily drawn to scale.
One problem with the prior art switching circuit shown in FIG. 1A is that during the transition from a low VIN (e.g., logical 0) to a high VIN (e.g., logical 1) the Vout node 124 is initially biased, along with the gate of depletion mode NFET 106, to (Vcc−Vtn) as discussed above. The presence of (Vcc−Vtn) on the gate of the depletion mode NFET 106, causes node 128 to be initially biased to VNODE128=(|Vtd|+Vcc−Vtn) where Vtd is the threshold voltage of the depletion mode NFET 106. If the voltage at node 128 is less than the threshold voltage (Vtp) of the enhancement mode PFET 104, the enhancement mode PFET 104 will be cut off and will not allow the Vout node 124 to be pulled up to Vpp 108 resulting in an operation failure of the circuit. During this failure scenario, the final output level of Vout node 124 might never reach Vpp 108 and may not rise above the level (Vcc−Vtn) 130 shown in FIG. 1B. For example, Vout 124 might not rise above 2.3V (e.g., 3V-0.7V) instead of rising to the desired level of Vpp 108. This problem can be aggravated by a trend to reduce the operating voltages (e.g., Vcc) and/or the need to use higher power handling transistors (e.g., which may have higher threshold voltages) used in many semiconductor devices, including such devices as non-volatile FLASH memory devices, for example.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a level shifting circuit having improved operating characteristics.